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| www..com RTL8111B INTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESSTM APPLICATIONS .com DataShee DATASHEET Rev. 1.1 24 March 2005 Track ID: JATR-1076-21 .com DataSheet 4 U .com www..com RTL8111B Datasheet COPYRIGHT (c)2005 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document "as is", without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the software engineer's reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process. t4U.com .com DataShee REVISION HISTORY Revision 1.0 1.1 Release Date 2005/01/17 2005/03/24 Summary First release. Changed Table 8, Power & Ground, page 6. Added lead (Pb)-free package identification information on page 3 and on page 27. Integrated Gigabit Ethernet Controller for PCI Express ii Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet Table of Contents 1. 2. 3. 4. 5. General Description .................................................................................................... 1 Features ........................................................................................................................ 2 System Applications .................................................................................................... 2 Pin Assignments........................................................................................................... 3 4.1. 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. 5.8. 5.9. 5.10. LEAD (PB)-FREE PACKAGE IDENTIFICATION ....................................................................................3 POWER MANAGEMENT/ISOLATION...................................................................................................4 PCI EXPRESS INTERFACE .................................................................................................................4 EEPROM.........................................................................................................................................4 TRANSCEIVER INTERFACE ................................................................................................................5 CLOCK..............................................................................................................................................5 REGULATOR & REFERENCE..............................................................................................................5 LEDS ...............................................................................................................................................5 POWER & GROUND ..........................................................................................................................6 NC (NOT CONNECTED) PINS ............................................................................................................6 SPI (SERIAL PERIPHERAL INTERFACE) FLASH PINS .........................................................................6 Pin Descriptions........................................................................................................... 4 6. t4U.com Functional Description................................................................................................ 7 6.1. 6.1.1. 6.1.2. PCI Express Transmitter.........................................................................................................................................7 PCI Express Receiver .............................................................................................................................................7 .com PCI EXPRESS BUS INTERFACE..........................................................................................................7 DataShee 6.2. 6.2.1. 6.2.2. 6.2.3. 6.2.4. 6.2.5. LED FUNCTIONS ..............................................................................................................................7 Link Monitor...........................................................................................................................................................7 Rx LED ...................................................................................................................................................................8 Tx LED ...................................................................................................................................................................8 Tx/Rx LED ..............................................................................................................................................................9 LINK/ACT LED ....................................................................................................................................................10 6.3. 6.3.1. 6.3.2. PHY TRANSCEIVER........................................................................................................................11 PHY Transmitter ................................................................................................................................................... 11 PHY Receiver........................................................................................................................................................ 11 6.4. 6.5. 6.6. 6.7. 6.8. NEXT PAGE ....................................................................................................................................12 EEPROM INTERFACE ....................................................................................................................12 POWER MANAGEMENT ...................................................................................................................13 VITAL PRODUCT DATA (VPD) .......................................................................................................15 SPI FLASH INTERFACE ...................................................................................................................16 ABSOLUTE MAXIMUM RATINGS.....................................................................................................17 RECOMMENDED OPERATING CONDITIONS......................................................................................17 CRYSTAL REQUIREMENTS ..............................................................................................................17 THERMAL CHARACTERISTICS .........................................................................................................18 iii Track ID: JATR-1076-21 Rev. 1.1 7. Characteristics ........................................................................................................... 17 7.1. 7.2. 7.3. 7.4. Integrated Gigabit Ethernet Controller for PCI Express .com DataSheet 4 U .com www..com RTL8111B Datasheet 7.5. 7.6. 7.6.1. 7.6.2. DC CHARACTERISTICS ...................................................................................................................18 AC CHARACTERISTICS ...................................................................................................................19 Serial EEPROM Interface Timing ........................................................................................................................19 SPI Flash Interface Timing...................................................................................................................................21 7.7. 7.7.1. 7.7.2. 7.7.3. 7.7.4. PCI EXPRESS BUS PARAMETERS ....................................................................................................23 Differential Transmitter Parameters.....................................................................................................................23 Differential Receiver Parameters .........................................................................................................................24 REFCLK Parameters............................................................................................................................................24 Auxiliary Signal Timing Parameters ....................................................................................................................26 8. 9. Mechanical Dimensions ............................................................................................ 27 Ordering Information ............................................................................................... 27 List of Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. t4U.com Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Power Management/Isolation......................................................................................................4 PCI Express Interface..................................................................................................................4 EEPROM.....................................................................................................................................4 Transceiver Interface...................................................................................................................5 Clock ...........................................................................................................................................5 Regulator & Reference................................................................................................................5 LEDs............................................................................................................................................5 DataShee .com Power & Ground .........................................................................................................................6 NC (Not Connected) Pins............................................................................................................6 SPI Flash Pins .............................................................................................................................6 EEPROM Interface ...................................................................................................................12 SPI Flash Interface ....................................................................................................................16 Absolute Maximum Ratings .....................................................................................................17 Recommended Operating Conditions .......................................................................................17 Crystal Requirements ................................................................................................................17 Thermal Characteristics ............................................................................................................18 DC Characteristics ....................................................................................................................18 EEPROM Access Timing Parameters.......................................................................................20 SPI Flash Timing Parameters....................................................................................................22 Differential Transmitter Parameters..........................................................................................23 Differential Receiver Parameters ..............................................................................................24 REFCLK Parameters.................................................................................................................24 Auxiliary Signal Timing Parameters.........................................................................................26 Ordering Information ................................................................................................................27 Integrated Gigabit Ethernet Controller for PCI Express iv Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Pin Assignments.........................................................................................................................3 Rx LED ......................................................................................................................................8 Tx LED ......................................................................................................................................8 Tx/Rx LED.................................................................................................................................9 LINK/ACT LED ......................................................................................................................10 Serial EEPROM Interface Timing ...........................................................................................19 Synchronous Data Timing .......................................................................................................21 WREN Timing .........................................................................................................................21 Read Timing.............................................................................................................................21 Program Timing.......................................................................................................................22 Sector/Chip Erase Timing........................................................................................................22 REFCLK Single-Ended Measurement Points for Trise and Tfall ...............................................25 REFCLK Single-Ended Measurement Points for Vovs, Vuds, and Vrb ......................................25 REFCLK Differential Measurement Points for Tperiod, Duty Cycle, and Jitter........................25 REFCLK Vcross Range .............................................................................................................26 Auxiliary Signal Timing ..........................................................................................................26 t4U.com .com DataShee Integrated Gigabit Ethernet Controller for PCI Express v Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 1. General Description The Realtek RTL8111B Gigabit Ethernet controller combines a triple-speed IEEE 802.3 compliant Media Access Controller (MAC) with a triple-speed Ethernet transceiver, PCI Express bus controller, and embedded memory. With state-of-the-art DSP technology and mixed-mode signal technology, the RTL8111B offers high-speed transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as Crossover Detection & Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are implemented to provide robust transmission and reception capability at high speeds. The device supports the PCI Express 1.0a bus interface for host communications with power management and is compliant with the IEEE 802.3u specification for 10/100Mbps Ethernet and the IEEE 802.3ab specification for 1000Mbps Ethernet. It also supports an auxiliary power auto-detect function, and will auto-configure related bits of the PCI power management registers in PCI configuration space. The RTL8111B supports the attachment of a 64Kbyte external Serial Peripheral Interface (SPI) Flash. The AT25F512 interface permits the RTL8111B to read from, and write data to, an external SPI Flash device and provides 64Kbytes of serial reprogrammable Flash memory. Advanced Configuration Power management Interface (ACPI)--power management for modern operating systems that are capable of Operating System-directed Power Management (OSPM)--is supported to achieve the most efficient power management possible. PCI Message Signaled Interrupt (MSI) is also supported. .com t4U.com DataShee In addition to the ACPI feature, remote wake-up (including AMD Magic PacketTM, Re-LinkOk, and Microsoft(R) Wake-up frame) is supported in both ACPI and APM (Advanced Power Management) environments. To support WOL from a deep power down state (e.g., D3cold, i.e. main power is off and only auxiliary exists), the auxiliary power source must be able to provide the needed power for the RTL8111B. The RTL8111B is fully compliant with Microsoft(R) NDIS5 (IP, TCP, UDP) Checksum and Segmentation Task-offload features, and supports IEEE 802 IP Layer 2 priority encoding and IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The above features contribute to lowering CPU utilization, especially benefiting performance when in operation on a network server. The device also features next-generation inter-connect PCI Express technology. PCI Express is a high-bandwidth, low pin count, serial, interconnect technology that offers significant improvements in performance over conventional PCI and also maintains software compatibility with existing PCI infrastructure. The RTL8111B is suitable for multiple market segments and emerging applications, such as desktop, mobile, workstation, server, communications platforms, and embedded applications. Integrated Gigabit Ethernet Controller for PCI Express 1 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 2. Features Integrated 10/100/1000 transceiver Auto-Negotiation with Next Page capability Supports PCI ExpressTM 1.0a Supports pair swap/polarity/skew correction Crossover Detection & Auto-Correction Wake-on-LAN and remote wake-up support Microsoft(R) NDIS5 Checksum Offload (IP, TCP, UDP) and Largesend Offload support Supports Full Duplex flow control (IEEE 802.3x) Fully compliant with IEEE 802.3, IEEE 802.3u, IEEE 802.3ab Supports IEEE 802.1P Layer 2 Priority Encoding Supports IEEE 802.1Q VLAN tagging Serial EEPROM SPI Flash Interface Transmit/Receive on-chip buffer (48KB) support Supports power down/link down power saving Supports PCI Message Signaled Interrupt (MSI) 64-pin QFN package t4U.com .com DataShee 3. System Applications PCI ExpressTM Gigabit Ethernet on Motherboard, Notebook, or Embedded system Integrated Gigabit Ethernet Controller for PCI Express 2 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 4. Pin Assignments VCTRL15 AVDD33 CKTAL2 CKTAL1 VDD15 VDD33 VDD15 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDD15 RSET GVDD LED0 LED1 LED2 LED3 TCLK TD VCTRL18 AVDD33 MDIP0 MDIN0 AVDD18 MDIN1 MDIP1 AVDD18 MDIP2 MDIN2 AVDD18 1 2 3 4 5 6 7 8 9 48 47 46 45 44 43 EESK EEDI/AUX VDD33 EEDO EECS VDD15 SPICSB VDD15 SPISCK TCS VDD15 VDD33 ISOLATEB SPISI SPISO VDD15 RTL8111B 42 41 40 39 10 11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 t4U.com MDIN3 MDIP3 AVDD18 VDD15 VDD33 LLLLLLL .com 38 37 36 35 34 32 33 TXXXV DataShee LANWAKEB PERSTB EGND EVDD18 EVDD18 REFCLK_P REFCLK_N VDD15 HSON EGND HSOP HSIP HSIN NC NC Figure 1. Pin Assignments 4.1. Lead (Pb)-Free Package Identification Lead (Pb)-free package is indicated by an "L" in the location marked "T" in Figure 1. Integrated Gigabit Ethernet Controller for PCI Express 3 Track ID: JATR-1076-21 VDD15 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 5. Pin Descriptions S/T/S: O/D: Sustained Tri-State Open Drain The signal type codes below are used in the following tables: I: Input O: Output T/S: Tri-State bi-directional input/output pin 5.1. Power Management/Isolation Symbol LANWAKEB Type O/D Pin No 19 Table 1. Power Management/Isolation Description Power Management Event: Open drain, active low. Used to reactivate the PCI Express slot's main power rails and reference clocks. Isolate Pin: Active low. Used to isolate the RTL8111B from the PCI Express bus. The RTL8111B will not drive its PCI Express outputs (excluding LANWAKEB) and will not sample its PCI Express input as long as the Isolate pin is asserted. ISOLATEB I 36 5.2. PCI Express Interface Symbol REFCLK_P REFCLK_N HSOP HSON HSIP HSIN PERSTB Type I I O O I I I Pin No 26 27 29 30 23 24 20 Table 2. PCI Express Interface Description PCI Express Differential Reference Clock Source: 100MHz 300ppm. .com PCI Express Transmit Differential Pair. t4U.com DataShee PCI Express Receive Differential Pair. PCI Express Reset Signal: Active low. When the PERSTB is asserted at power-on state, the RTL8111B returns to a pre-defined reset state and is ready for initialization and configuration after the de-assertion of the PERSTB. 5.3. EEPROM Symbol EESK Type O Pin No 48 Table 3. EEPROM Description Serial data clock. EEDI: Output to serial data input pin of EEPROM. AUX: Input pin to detect if Aux. Power exists or not on initial power-on. This pin should be connected to EEPROM. To support wakeup from ACPI D3cold or APM power-down, this pin must be pulled high to Aux. Power via a resistor. If this pin is not pulled high to Aux. Power, the RTL8111B assumes that no Aux. Power exists. Input from serial data output pin of EEPROM. EECS: EEPROM chip select. 4 Track ID: JATR-1076-21 Rev. 1.1 EEDI/AUX O/I 47 EEDO EECS I O 45 44 Integrated Gigabit Ethernet Controller for PCI Express .com DataSheet 4 U .com www..com RTL8111B Datasheet 5.4. Transceiver Interface Symbol MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3 Type I/O I/O I/O I/O I/O I/O I/O I/O 9 10 13 12 7 6 Pin No 3 4 Table 4. Transceiver Interface Description In MDI mode, this is the first pair in 1000Base-T, i.e. the BI_DA+/- pair, and is the transmit pair in 10Base-T and 100Base-TX. In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the receive pair in 10Base-T and 100Base-TX. In MDI mode, this is the second pair in 1000Base-T, i.e. the BI_DB+/- pair, and is the transmit pair in 10Base-T and 100Base-TX. In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the transmit pair in 10Base-T and 100Base-TX. In MDI mode, this is the third pair in 1000Base-T, i.e. the BI_DC+/- pair. In MDI crossover mode, this pair acts as the BI_DD+/- pair. In MDI mode, this is the fourth pair in 1000Base-T, i.e. the BI_DD+/- pair. In MDI crossover mode, this pair acts as the BI_DC+/- pair. 5.5. Clock Symbol CKXTAL1 CKXTAL2 Type I O Pin No 60 61 Table 5. Clock Description Input of 25MHz clock reference. Output of 25MHz clock reference. t4U.com 5.6. Regulator & Reference .com Symbol VCTRL15 VCTRL18 RSET Type O O I Pin No 63 1 64 Table 6. Regulator & Reference Description Regulator Control. Voltage control to external 1.5V power transistor. Regulator Control. Voltage control to external 1.8V power transistor. Reference. External resistor reference. DataShee 5.7. LEDs Table 7. Symbol LED0 LED1 LED2 Type O O O Pin No 57 56 55 Description LEDS1-0 LED0 LED1 LED3 O 54 LED2 LED3 00 Tx/Rx LINK100 LINK10 LINK1000 LEDs 01 LINK10/1000/ ACT LINK100/1000/ ACT FULL LINK1000 10 Tx LINK Rx FULL 11 LINK10/ACT LINK100/ ACT FULL LINK1000/ ACT Note 1: During power down mode, the LED signals are logic high. Note 2: LEDS1-0's initial value comes from the 93C46. If there is no 93C46, the default value of the (LEDS1, LEDS0) = (1, 1). Integrated Gigabit Ethernet Controller for PCI Express 5 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 5.8. Power & Ground Table 8. Power & Ground Pin No Description 16, 37, 46, 53 Digital 3.3V power supply. 15, 21, 32, 33, 38, 41, VDD15 Power Digital 1.5V power supply. 43, 49, 52, 58 AVDD18 Power 5, 8, 11, 14 Analog 1.8V power supply. EVDD18 Power 22, 28 Analog 1.8V power supply. GVDD O 62 Output 1.5V. AVDD33 Power 2, 59 Analog 3.3V power supply. EGND Power 25, 31 Analog Ground. Note 1: GVDD is tied to the internal 1.5V power supply. Do not connect this pin to any other power supply. Connect only to two capacitors. Note 2: Refer to the most updated schematic circuit for correct configuration. Symbol VDD33 Type Power 5.9. NC (Not Connected) Pins Symbol NC Type Table 9. Pin No 17, 18 NC (Not Connected) Pins Description Not Connected. 5.10. SPI (Serial Peripheral Interface) Flash Pins t4U.com Symbol SPISO SPISI SPISCK SPICSB Type I O O O Pin No 34 35 40 42 Table 10. SPI Flash Pins .com Description Input from serial data output pin of SPI Flash. Output to serial data input pin of SPI Flash. Serial data clock. SPI Flash chip select. DataShee Integrated Gigabit Ethernet Controller for PCI Express 6 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 6. Functional Description 6.1. PCI Express Bus Interface The RTL8111B is compliant with PCI Express Base Specification Revision 1.0a, and runs at a 2.5GHz signaling rate with X1 link width, i.e., one transmit and one receive differential pair. The RTL8111B supports four types of PCI Express messages: interrupt messages, error messages, power management messages, and hot-plug messages. To ease PCB layout constraints, PCI Express lane polarity reversal and link reversal are also supported. 6.1.1. PCI Express Transmitter The RTL8111B's PCI Express block receives digital data from the Ethernet interface and performs data scrambling with Linear Feedback Shift Register (LFSR) and 8B/10B coding technology into 10-bit code groups. Data scrambling is used to reduce the possibility of electrical resonance on the link, and 8B/10B coding technology is used to benefit embedded clocking, error detection, and DC balance by adding an overhead to the system through the addition of 2 extra bits. The data code groups are passed through its serializer for packet framing. The generated 2.5Gbps serial data is transmitted onto the PCB trace to its upstream device via a differential driver. 6.1.2. PCI Express Receiver The RTL8111B's PCI Express block receives 2.5Gbps serial data from its upstream device to generate parallel data. The receiver's PLL circuits are re-synchronized to maintain bit and symbol lock. Through .com t4U.com aShee 8B/10B decoding technology and data descrambling, the original digital data is recovered and passed to Dat the RTL8111B's internal Ethernet MAC to be transmitted onto the Ethernet media. 6.2. LED Functions The RTL8111B supports four LED signals in four different configurable operation modes. The following sections describe the various LED actions. 6.2.1. Link Monitor The Link Monitor senses link integrity, such as LINK10, LINK100, LINK1000, LINK10/100/1000, LINK10/ACT, LINK100/ACT, or LINK1000/ACT. Whenever link status is established, the specific link LED pin is driven low. Once a cable is disconnected, the link LED pin is driven high, indicating that no network connection exists. Integrated Gigabit Ethernet Controller for PCI Express 7 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 6.2.2. Rx LED Power On In 10/100/1000Mbps mode, blinking of the Rx LED indicates that receive activity is occurring. LED = High Receiving Packet? Yes No LED = High for 40 ms LED = Low for 40 ms Figure 2. Rx LED 6.2.3. t4U.com Tx LED In 10/100/1000Mbps mode, blinking of the Tx LED indicates that transmit activity is occurring. Power On .com DataShee LED = High Transmitting Packet? Yes No LED = High for 40 ms LED = Low for 40 ms Figure 3. Integrated Gigabit Ethernet Controller for PCI Express 8 Tx LED Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 6.2.4. Tx/Rx LED In 10/100/1000Mbps mode, blinking of the Tx/Rx LED indicates that both transmit and receive activity is occurring. Power On LED = High Tx/Rx Packet? Yes No LED = High for 40 ms LED = Low for 40 ms t4U.com Figure 4. Tx/Rx LED .com DataShee Integrated Gigabit Ethernet Controller for PCI Express 9 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 6.2.5. LINK/ACT LED In 10/100/1000Mbps mode, blinking of the LINK/ACT LED indicates that the RTL8111B is linked and operating properly. When this LED is high for extended periods, it indicates that a link problem exists. Power On LED = High Link? Yes LED = Low No No Tx/Rx Packet? Yes .com LED = High for 40 ms t4U.com DataShee LED = Low for 40 ms Figure 5. LINK/ACT LED Integrated Gigabit Ethernet Controller for PCI Express 10 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 6.3. PHY Transceiver 6.3.1. PHY Transmitter Based on state-of-the-art DSP technology and mixed-mode signal processing technology, the RTL8111B operates at 10/100/1000Mbps over standard CAT.5 UTP cable (100/1000Mbps), and CAT.3 UTP cable (10Mbps). GMII (1000Mbps) Mode The RTL8111B's PCS layer receives data bytes from the MAC through the GMII interface and performs the generation of continuous code-groups through 4D-PAM5 coding technology. These code groups are passed through a waveform-shaping filter to minimize EMI effect, and are transmitted onto the 4-pair CAT5 cable at 125MBaud/s through a D/A converter. MII (100Mbps) Mode The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25MHz (TXC), are converted into 5B symbol code through 4B/5B coding technology, then through scrambling and serializing, are converted to 125Mhz NRZ and NRZI signals. After that, the NRZI signals are passed to the MLT3 encoder, then to the D/A converter and transmitted onto the media. MII (10Mbps) Mode The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into 10Mbps serial data. The 10Mbps serial data is converted into a Manchester-encoded data stream and is transmitted onto the media by the D/A converter. .com t4U.com 6.3.2. PHY Receiver DataShee GMII (1000Mbps) Mode Input signals from the media pass through the sophisticated on-chip hybrid circuit to subtract the transmitted signal from the input signal for effective reduction of near-end echo. Afterwards, the received signal is processed with state-of-the-art technology, e.g., adaptive equalization, BLW (Baseline Wander) correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5 decoding. Then, the 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz. The Rx MAC retrieves the packet data from the receive MII/GMII interface and sends it to the Rx Buffer Manager. MII (100Mbps) Mode The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing recovery, MLT3 and NRZI decoder, descrambler, 4B/5B decoder, and is then presented to the MII interface in 4-bit-wide nibbles at a clock speed of 25MHz. MII (10Mbps) Mode The received differential signal is converted into a Manchester-encoded stream first. Next, the stream is processed with a Manchester decoder and is de-serialized into 4-bit-wide nibbles. The 4-bit nibbles are presented to the MII interface at a clock speed of 2.5MHz. Integrated Gigabit Ethernet Controller for PCI Express 11 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 6.4. Next Page If 1000Base-T mode is advertised, three additional Next Pages are automatically exchanged between the two link partners. Users can set PHY Reg4.15 to 1 to manually exchange extra Next Pages via Reg7 and Reg8 as defined in IEEE 802.3ab. 6.5. EEPROM Interface The RTL8111B requires the attachment of an external EEPROM. The 93C46/93C56 is a 1K-bit/2K-bit EEPROM. The EEPROM interface permits the RTL8111B to read from, and write data to, an external serial EEPROM device. Values in the external EEPROM allow default fields in PCI configuration space and I/O space to be overridden following a power-on or software EEPROM auto-load command. The RTL8111B will auto-load values from the EEPROM. If the EEPROM is not present, the RTL8111B initialization uses default values for the appropriate Configuration and Operational Registers. Software can read and write to the EEPROM using bit-bang accesses via the 9346CR Register, or using PCI VPD (Vital Product Data). The interface consists of EESK, EECS, EEDO, and EEDI. The correct EEPROM (i.e. 93C46/93C56) must be used in order to ensure proper LAN function. Table 11. EEPROM Interface Description 93C46/93C56 chip select. EEPROM serial data clock. Input data bus/Input.com Aux. Power exists on initial power-on. pin to detect whether This pin should be connected to EEPROM. To support wakeup from ACPI D3cold or APM power-down, this pin must be pulled high to Aux. Power via a resistor. If this pin is not pulled high to Aux. Power, the RTL8111B assumes that no Aux. Power exists. Output data bus. EEPROM EECS EESK t4U.com DataShee EEDI/Aux EEDO Integrated Gigabit Ethernet Controller for PCI Express 12 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 6.6. Power Management The RTL8111B is compliant with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), PCI Express Active State Power Management (ASPM), and Network Device Class Power Management Reference Specification (V1.0a), such as to support an Operating System-directed Power Management (OSPM) environment. The RTL8111B can monitor the network for a Wakeup Frame, a Magic Packet, or a Re-LinkOk, and notify the system via a PCI Express Power Management Event (PME) Message, Beacon, or LANWAKEB pin when such a packet or event occurs. Then the system can be restored to a normal state to process incoming jobs. When the RTL8111B is in power down mode (D1 ~ D3): * The Rx state machine is stopped. The RTL8111B monitors the network for wakeup events such as a Magic Packet, Wakeup Frame, and/or Re-LinkOk, in order to wake up the system. When in power down mode, the RTL8111B will not reflect the status of any incoming packets in the ISR register and will not receive any packets into the Rx on-chip buffer. * The on-chip buffer status and packets that have already been received into the Rx on-chip buffer before entering power down mode are held by the RTL8111B. * Transmission is stopped. PCI Express transactions are stopped. The Tx on-chip buffer is held. * After being restored to D0 state, the RTL8111B transmits data that was not moved into the Tx on-chip buffer during power down mode. Packets that were not transmitted completely last time are re-transmitted. t4U.com .com DataShee The D3cold_support_PME bit (bit15, PMC register) and the Aux_I_b2:0 bits (bit8:6, PMC register) in PCI configuration space depend on the existence of Aux power (bit15, PMC) = 1. If EEPROM D3cold_support_PME bit (bit15, PMC) = 0, the above 4 bits are all 0's. Example: If EEPROM D3c_support_PME = 1: * If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C2 F7, then PCI PMC = C2 F7) * If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0's (if EEPROM PMC = C2 F7, then PCI PMC = 02 76) In the above case, if wakeup support is desired when main power is off, it is suggested that the EEPROM PMC be set to C2 F7 (Realtek EEPROM default value). If EEPROM D3c_support_PME = 0: * If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C2 77, then PCI PMC = C2 77) * If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0's (if EEPROM PMC = C2 77, then PCI PMC = 02 76) In the above case, if wakeup support is not desired when main power is off, it is suggested that the EEPROM PMC be set to 02 76. Integrated Gigabit Ethernet Controller for PCI Express 13 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet Link Wakeup occurs only when the following conditions are met: * The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the corresponding wake-up method (message, beacon, or LANWAKEB) can be asserted in the current power state. Magic Packet Wakeup occurs only when the following conditions are met: * The destination address of the received Magic Packet is acceptable to the RTL8111B, e.g., a broadcast, multicast, or unicast packet addressed to the current RTL8111B adapter. * The received Magic Packet does not contain a CRC error. * The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the corresponding wake-up method (message, beacon, or LANWAKEB) can be asserted in the current power state. * The Magic Packet pattern matches, i.e. 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in any part of a valid Ethernet packet. A Wakeup Frame event occurs only when the following conditions are met: * The destination address of the received Wakeup Frame is acceptable to the RTL8111B, e.g., a broadcast, multicast, or unicast address to the current RTL8111B adapter. * The received Wakeup Frame does not contain a CRC error. * The PMEn bit (CONFIG1#0) is set to 1. * The 16-bit CRCA of the received Wakeup Frame matches the 16-bit CRC of the sample Wakeup Frame pattern given by the local machine's OS. Or, the RTL8111B is configured to allow direct packet .com t4U.com DataShee wakeup, e.g., a broadcast, multicast, or unicast network packet. Note: 16-bit CRC: The RTL8111B supports two normal wakeup frames (covering 64 mask bytes from offset 0 to 63 of any incoming network packet) and three long wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet). The corresponding wake-up method (message, beacon, or LANWAKEB) is asserted only when the following conditions are met: * The PMEn bit (bit0, CONFIG1) is set to 1. * The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1. * The RTL8111B may assert the corresponding wake-up method (message, beacon, or LANWAKEB) in the current power state or in isolation state, depending on the PME_Support (bit15-11) setting of the PMC register in PCI Configuration Space. * A Magic Packet, LinkUp, or Wakeup Frame has been received. * Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears this bit and causes the RTL8111B to stop asserting the corresponding wake-up method (message, beacon, or LANWAKEB) (if enabled). Integrated Gigabit Ethernet Controller for PCI Express 14 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet When the RTL8111B is in power down mode, e.g., D1-D3, the IO and MEM accesses to the RTL8111B are disabled. After a PERSTB assertion, the device's power state is restored to D0 automatically if the original power state was D3cold. There is almost no hardware delay at the device's power state transition. When in ACPI mode, the device does not support PME (Power Management Enable) from D0 (this is the Realtek default setting of the PMC register auto-loaded from EEPROM). The setting may be changed from the EEPROM, if required. 6.7. Vital Product Data (VPD) Bit 31 of the Vital Product Data (VPD) capability structure in the RTL8111B's PCI Configuration Space is used to issue VPD read/write commands and is also a flag used to indicate whether the transfer of data between the VPD data register and the 93C46/93C56 has completed or not. 1. Write VPD register: (write data to the 93C46/93C56) Set the flag bit to 1 at the same time the VPD address is written to write VPD data to EEPROM. When the flag bit is reset to 0 by the RTL8111B, the VPD data (4 bytes per VPD access) has been transferred from the VPD data register to EEPROM. 2. Read VPD register: (read data from the 93C46/93C56) Reset the flag bit to 0 at the same time the VPD address is written to retrieve VPD data from EEPROM. When the flag bit is set to 1 by the RTL8111B, the VPD data (4 bytes per VPD access) has been transferred from EEPROM to the VPD data register. Note1: Refer to the PCI 2.2 Specifications for further information. .com t4U.com Note2: The VPD address must be a DWORD-aligned address as defined in the PCI 2.2 Specifications. VPD data is always consecutive 4-byte data starting from the VPD address specified. DataShee Note3: Realtek reserves offset 40h to 7Fh in EEPROM mainly for VPD data to be stored. Note4: The VPD function of the RTL8111B is designed to be able to access the full range of the 93C46/93C56 EEPROM. Integrated Gigabit Ethernet Controller for PCI Express 15 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 6.8. SPI Flash Interface The RTL8111B supports the attachment of a 64Kbyte external Serial Peripheral Interface (SPI) Flash. The AT25F512 provides 64Kbytes of serial reprogrammable Flash memory. SPI Flash is enabled by the RTL8111B through the Chip Select pin, and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The AT25F512/1024 utilizes an 8-bit instruction register. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low transition. Instead of a parallel bus interface, the Serial Peripheral Interface provides simpler wiring and much less interaction (crosstalk) among the conductors in the cable. This minimizes the number of conductors, pins, and the IC package size, reducing the cost of making, assembling, and testing the electronics. SPI Flash SO SI SCK CS Table 12. SPI Flash Interface Description Input data bus. Output data bus. SPI Flash serial data clock. SPI Flash chip select. t4U.com .com DataShee Integrated Gigabit Ethernet Controller for PCI Express 16 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 7. Characteristics 7.1. Absolute Maximum Ratings WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to the device, or device reliability will be affected. All voltages are specified reference to GND unless otherwise specified. Table 13. Absolute Maximum Ratings Symbol Description Minimum Maximum VDD3, HV1VDD Supply Voltage 3.3V -0.5 4.6 V0VDD Supply Voltage 2.5V -0.5 3 VDD1A Supply Voltage 1.8V -0.5 2.1 LVVDD Supply Voltage V* VDD1 Supply Voltage 1.5V -0.5 2 DCinput Input Voltage -0.5 Corresponding Supply Voltage + 0.5 DCoutput Output Voltage -0.5 Corresponding Supply Voltage + 0.5 Storage Temperature -55 +125 * Refer to the most updated schematic circuit for correct configuration. Unit V V V V V V C 7.2. Recommended Operating Conditions Description Table 14. Recommended Operating Conditions Pins Minimum Typical VDD3, HV1VDD 3.0 3.3 V0VDD 2. 25 2.5 .com VDD1A 1.71 1.8 LVVDD * VDD1 1.425 1.5 0 Maximum 3.6 2.75 1.89 1.575 70 125 Unit V V V V V C C t4U.com Supply Voltage VDD DataShee Ambient Temperature TA Maximum Junction Temperature * Refer to the most updated schematic circuit for correct configuration. 7.3. Crystal Requirements Symbol Fref Fref Stability Fref Tolerance Fref Duty Cycle CL ESR DL Table 15. Crystal Requirements Description/Condition Minimum Parallel resonant crystal reference frequency, fundamental mode, AT-cut type. Parallel resonant crystal frequency stability, -50 fundamental mode, AT-cut type. Ta=25C. Parallel resonant crystal frequency tolerance, fundamental mode, AT-cut type. -30 Ta=-20C ~+70C. Reference clock input duty cycle. Load Capacitance. Equivalent Series Resistance. Drive Level. 17 40 Typical 25 +50 +30 60 Maximum Unit MHz ppm ppm % pF mW Rev. 1.1 0.5 Track ID: JATR-1076-21 Integrated Gigabit Ethernet Controller for PCI Express .com DataSheet 4 U .com www..com RTL8111B Datasheet 7.4. Thermal Characteristics Parameter Storage Temperature Operating Ambient Temperature Table 16. Thermal Characteristics Minimum Maximum -55 +125 0 70 Units C C 7.5. DC Characteristics Symbol VDD3, HV1VDD V0VDD VDD1A, LVVDD VDD1 Voh Vol Vih Vil t4U.com Parameter 3.3V Supply Voltage 2.5V Supply Voltage 1.8V Supply Voltage Supply Voltage* 1.5V Supply Voltage Minimum High Level Output Voltage Maximum Low Level Output Voltage Minimum High Level Input Voltage Maximum Low Level Input Voltage Input Current Table 17. DC Characteristics Conditions Minimum Typical 3.0 2.25 1.71 1.425 Ioh = -8mA Iol= 8mA 0.5 * VDD3 -0.5 .com Vin = VDD3 or -1.0 GND TBD 0.9 * VDD3 3.3 2.5 1.8 1.5 Maximum 3.6 2.75 1.89 1.575 VDD3 0.1 * VDD3 VDD3+0.5 0.3 * VDD3 1.0 Units V V V V V V V V V A mA Iin Icc33 DataShee Average Operating Supply Current from 3.3V Average Operating Icc25 Supply Current from 2.5V Average Operating Icc18 Supply Current from 1.8V Average Operating Icc15 Supply Current from 1.5V * Refer to the most updated schematic circuit for correct configuration. TBD mA TBD mA TBD mA Integrated Gigabit Ethernet Controller for PCI Express 18 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 7.6. AC Characteristics 7.6.1. EESK EECS EEDI (Read) (Read) Serial EEPROM Interface Timing 93C46(64*16)/93C56(128*16) tcs 1 1 0 An A2 A1 A0 0 Dn D1 D0 EEDO High Impedance EESK EECS EEDI (Write) (Write) tcs 1 0 1 An ... A0 Dn ... D0 BUSY twp READY EEDO High Impedance tsk t4U.com EESK .com tskh tcss tdis tdih tdos tdoh tskl tcsh DataShee EECS EEDI EEDO (Read) EEDO tsv (Program) STATUS VALID Figure 6. Serial EEPROM Interface Timing Integrated Gigabit Ethernet Controller for PCI Express 19 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet Symbol tcs twp tsk tskh tskl tcss tcsh tdis tdih tdos tdoh tsv Table 18. EEPROM Access Timing Parameters Parameter EEPROM Type Min. Minimum CS Low Time 9346 1000 Write Cycle Time 9346 SK Clock Cycle Time 9346 4 SK High Time 9346 1000 SK Low Time 9346 1000 CS Setup Time 9346 200 CS Hold Time 9346 0 DI Setup Time 9346 400 DI Hold Time 9346 400 DO Setup Time 9346 2000 DO Hold Time 9346 CS to Status Valid 9346 Max. 10 Unit ns ms s ns ns ns ns ns ns ns ns ns 2000 1000 t4U.com .com DataShee Integrated Gigabit Ethernet Controller for PCI Express 20 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 7.6.2. SPI Flash Interface Timing SPICS V SPISCK VIH IL t CS VIH VIL VIH IL t CSS tWH t SU VALID IN t WL t CSH tH tV t HO t DIS HI-Z SPISI V SPISO V VIH IL HI-Z Figure 7. Synchronous Data Timing SPICS SPISCK SPISI t4U.com WREN OP-CODE .com HI-Z SPISO DataShee Figure 8. WREN Timing SPICS 0 12 345 6 78 9 10 11 28 29 30 31 32 33 34 35 36 37 38 39 SPISCK 3-BYTE ADDRESS SPISI SPISO INSTRUCTION 23 22 21 20 3210 HIGH IMPEDANCE 76543210 Figure 9. Read Timing Integrated Gigabit Ethernet Controller for PCI Express 21 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet SPICS 2077 2 2078 1 0 12 345 6 78 9 10 11 28 29 30 31 32 33 34 2079 0 SPISCK 3-BYTE ADDRESS 1st BYTE DATA-IN 0 7 6 SPISI SPISO INSTRUCTION 23 22 21 3 2 1 HIGH IMPEDANCE 256th BYTE DATA-IN Figure 10. Program Timing SPICS Sector Erase Timing 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 Chip Erase Timing 01234567 SPISCK INSTRUCTION 3-BYTE ADDRESS 3210 INSTRUCTION 011 0X0 10 SPISI SPISO t4U.com 0101 X 0 1 0 23 22 21 HIGH IMPEDANCE Figure 11. .com Timing Sector/Chip Erase Table 19. SPI Flash Timing Parameters Parameter Compatible Type Min SPICS Setup Time AT25F512 25 SPICS Hold Time AT25F512 25 SPICS High Time AT25F512 25 SPISCK High Time AT25F512 20 SPISCK Low Time AT25F512 20 Data In Setup Time AT25F512 5 Data In Hold Time AT25F512 5 Output Valid AT25F512 Output Hold Time AT25F512 0 Output Disable Time AT25F512 DataShee Symbol tCSS tCSH tCS tWH tWL tSU tH tV tHO tDIS Max 20 100 Unit ns ns ns ns ns ns ns ns ns ns Integrated Gigabit Ethernet Controller for PCI Express 22 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 7.7. PCI Express Bus Parameters 7.7.1. Differential Transmitter Parameters Table 20. Differential Transmitter Parameters Parameter Min Unit Interval2 399.88 Differential Peak to Peak Output Voltage 0.800 De-Emphasized Differential Output Voltage (Ratio) -3.0 Minimum Tx Eye Width 0.70 Maximum time between the jitter median and maximum deviation from the median D+/D- Tx Output Rise/Fall Time 0.125 RMS AC Peak Common Mode Output Voltage Absolute Delta of DC Common Mode Voltage During 0 L0 and Electrical Idle Absolute Delta of DC Common Mode Voltage between 0 D+ and DElectrical Idle Differential Peak Output Voltage 0 The amount of voltage change allowed during Receiver Detection The TX DC Common Mode Voltage 0 TX Short Circuit Current Limit Minimum time spent in Electrical Idle 50 Maximum time to transition to a valid Electrical Idle after sending an Electrical Idle ordered set Maximum time to transition to valid TX specifications .com after leaving an Electrical Idle condition Differential Return Loss 12 Common Mode Return Loss 6 DC Differential TX Impedance 80 Transmitter DC Impedance 40 Lane-to-Lane Output Skew Typical 400 -3.5 Max 400.12 1.2 -4.0 0.15 Units ps V dB UI UI UI mV mV mV mV mV V mA UI UI UI dB dB ps Symbol UI VTX-DIFFp-p VTX-DE-RATIO TTX-EYE TTX-EYE-MEDIANto-MAX-JITTER TTX-RISE, TTX-FALL VTX-CM-ACp VTX-CM-DCACTIVEIDLEDELTA 20 100 25 20 600 3.6 90 20 20 VTX-CM-DCLINEDELTA VTX-IDLE-DIFFp VTX-RCV-DETECT VTX-DC-CM ITX-SHORT TTX-IDLE-MIN TTX-IDLE- SETTO-IDLE t4U.com TTX-IDLE-TOTODIFF-DATA DataShee RLTX-DIFF RLTX-CM ZTX-DIFF-DC ZTX-DC LTX-SKEW 100 120 500+2 UI CTX AC Coupling Capacitor 75 200 nF Tcrosslink Crosslink Random Timeout 0 1 ms Note1: Refer to PCI Express Base Specification, rev.1.0a, for correct measurement environment setting of each parameter. Note2: The data rate can be modulated with an SSC (Spread Spectrum Clock) from +0 to -0.5% of the nominal data rate frequency, at a modulation rate in the range not exceeding 30 kHz - 33 kHz. The +/- 300 ppm requirement still holds, which requires the two communicating ports be modulated such that they never exceed a total of 600 ppm difference. Integrated Gigabit Ethernet Controller for PCI Express 23 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 7.7.2. Differential Receiver Parameters Table 21. Differential Receiver Parameters Symbol Parameter Min. Typical Max. Units UI Unit Interval 399.88 400 400.12 ps VRX-DIFFp-p Differential Input Peak to Peak Voltage 0.175 1.200 V TRX-EYE Minimum Receiver Eye Width 0.4 UI TRX-EYE-MEDIAN-toMaximum time between the jitter median and maximum 0.3 UI deviation from the median MAX-JITTER VRX-CM-ACp AC Peak Common Mode Input Voltage 150 mV RLRX-DIFF Differential Return Loss 15 dB RLRX-CM Common Mode Return Loss 6 dB ZRX-DIFF-DC DC Differential Input Impedance 80 100 120 ZRX--DC DC Input Impedance 40 50 60 ZRX-HIGH-IMP-DC Powered Down DC Input Impedance 200 k VRX-IDLE-DET-DIFFp-p Electrical Idle Detect Threshold 65 175 mV TRX-IDLE-DETUnexpected Electrical Idle Enter Detect Threshold 10 ms Integration Time DIFFENTERTIME LRX-SKEW Total Skew 20 ns Note: Refer to PCI Express Base Specification, rev.1.0a, for correct measurement environment setting of each parameter. 7.7.3. Symbol t4U.com REFCLK Parameters Table 22. REFCLK Parameters Parameter Min 9.872 175 175 100MHz Input Max Units .com Tabsmin Absolute min. DIF CLK Period ns Trise Rise Time 700 ps Tfall Fall Time 700 ps h Trise Rise Time Variation 125 ps Tfall Fall Time Variation 125 ps Rise/Fall Matching 20 % Vhigh Voltage High (typical 0.71V) 660 850 mV Vlow Voltage Low (typical 0.0V) -150 mV Vcross absolute Absolute Crossing Point Voltages 250 550 mV Vcross relative Relative Crossing Point Voltages Note2 Note2 V Total Vcross Total Variation of Vcross over all edges 140 mV Tccjitter Cycle to Cycle Jitter 125 ps Duty Cycle 45 55 % Vovs Maximum Voltage (Overshoot) Vhigh_avg + 0.3 V Vuds Minimum Voltage (Undershoot) -0.3 V Vrb Ringback Voltage 0.2 N/A V Note1: Refer to PCI Express Base Specification, rev.1.0a, for correct measurement environment setting of each parameter. Note2: Vcross relative Min = 0.5(Vhigh_avg - 0.710) + 0.250, Vcross relative Max = 0.5(Vhigh_avg - 0.710) + 0.550. The crossing point must meet the absolute and relative crossing point specifications simultaneously. Note3: The nominal single-ended swing for each clock is 0 to 0.7V with a nominal frequency of 100MHz 300 PPM. Note4: The reference clocks may support spread spectrum clocking. The minimum clock period cannot be violated. DataShee Integrated Gigabit Ethernet Controller for PCI Express 24 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet Figure 12. REFCLK Single-Ended Measurement Points for Trise and Tfall t4U.com .com Figure 13. REFCLK Single-Ended Measurement Points for Vovs, Vuds, and Vrb DataShee Figure 14. REFCLK Differential Measurement Points for Tperiod, Duty Cycle, and Jitter Integrated Gigabit Ethernet Controller for PCI Express 25 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet Figure 15. REFCLK Vcross Range 7.7.4. Symbol TPVPERL TPERST-CLK TPERST TFAIL TWKRF t4U.com Auxiliary Signal Timing Parameters Table 23. Auxiliary Signal Timing Parameters Parameter Min Power stable to PERSTB inactive 100 REFCLK stable before PERSTB inactive 100 PERSTB active time 100 Power level invalid to PWRGD inactive LANWAKEB rise - fall time .com Max 500 100 Units ms s s ns ns DataShee 3.3 Vaux 3.3/12V PERSTB REFCLK PCI-E Link Inactive Power Stable Wakeup Event Power Stable Clock Stable Clock not Stable Clock Stable Active T PVPERL T PERST-CLK Inactive T PERST T FAIL Active Figure 16. Auxiliary Signal Timing Integrated Gigabit Ethernet Controller for PCI Express 26 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com www..com RTL8111B Datasheet 8. Mechanical Dimensions t4U.com .com 9. Ordering Information Table 24. Ordering Information Part Number Package RTL8111B 64-Pin QFN RTL8111B-LF 64-Pin QFN Lead (Pb)-Free package Note: See page 3 for lead (Pb)-free package ID information. Status Realtek Semiconductor Corp. Headquarters No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 www.realtek.com.tw Integrated Gigabit Ethernet Controller for PCI Express 27 Track ID: JATR-1076-21 Rev. 1.1 .com DataSheet 4 U .com |
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